1. Technical Field
The present invention generally relates to electronic digital systems, and in particular to a method and apparatus for generating a bit stream for utilization in an electronic digital system. Still more particularly, the present invention relates to a method and apparatus for generating a controllable bit stream for utilization in logic verification of operations within an electronic digital system.
2. Description of the Related Art
The evolution of digital systems and circuit technology has led to systems of ever increasing complexity and physical density. This relentless pace of innovation has led to systems that are inherently difficult to verify before construction and/or validated by testing after construction.
The increased functional complexity of modern digital system leads to systems with extremely complicated functional behavior and large numbers of functional units. Within these numerous units, there are often paths and functions within the system that are utilized, on average, quite infrequently. Such portions of a digital system are typically difficult to verify during simulation and require intensive directed effort and manual testing in order to verify these functions. Often, simulation fails to adequately verify such infrequently-utilized functions which constitute the source of many design errors in modern digital systems. In addition, modern simulation techniques are several orders of magnitude slower than actual system operation. It would be advantageous to allow for exercising such paths, in a controllable manner, within a realized digital system to allow for greater validation of the digital system.
Further, increased circuit density results in structures, such as data arrays, that are more susceptible to errors induced by environmental sources such as naturally occurring alpha particles. To combat these issues, such data structures typically resort to some form of error correction or detection coding that detects the presence of errors and potentially allows for the correction of these errors. Such correction mechanisms form a specific subclass of infrequently utilized logic paths within a design. However, due to the fact that these mechanisms are rarely exercised and often uncontrollably exercised (i.e. the error is caused by a natural environmental process that is not directly controllable), it is difficult to validate, through laboratory testing, these error correction mechanisms. Simulation techniques can be utilized to simulate the naturally occurring error processes. Simulation, however, is typically several orders of magnitude slower than actual system operation.
It would therefore be a distinct advantage to have a method and apparatus that would allow for the controllable exercising of such infrequently or externally (environmentally) driven logic paths within a realized digital system to allow for greater validation of the system. The present invention provides such a method and apparatus.
It is therefore one object of the present invention to provide an improved electronic digital system.
It is another object of the present invention to provide a method and apparatus for generating a bit stream for utilization in an electronic digital system.
It is yet another object of the present invention to provide a method and apparatus for generating a controllable bit stream for utilization in logic verification of operations within an electronic digital system.
The foregoing objects are achieved as is now described. A system for controllable run-time verification of operations in a logic structure of a digital system is disclosed. The system comprises of a controllable bit stream generator having means for producing a controlled bit stream output. The controlled bit stream output corresponds to a bit sequence which instantiates a verification of operations within the logic structure. The system also comprises of means for coupling the controlled bit stream output to the logic structure and means for verifying the operations of the logic structure utilizing the controlled bit stream output.
In one embodiment, the system is utilized to verify the operations of an parity bit error correction sequencer which includes a data array coupled via a plurality of logic gates to an Error Correcting Code (ECC) encoder which detects and corrects a single bit error in data. The verification process includes instantiating the generation of a controlled bit stream output representing an error in data.
The above as well as additional objects, features, and advantages of an illustrative embodiment will become apparent in the following detailed written description.